Chip-to-chip wireline communication consists of a chip sending and receiving data from another chip over wires incorporated on a board on which the communicating chips are placed. The sending chip drives the data onto the wire, otherwise known as a board trace, using a driver circuit. The receiving chip receives the data at the other end of the communication bus using a receiver circuit. The unit of data transferred may be called a bit. A chip may use a single wire to send data, wherein the communication method is called single-ended signaling, or it may use a pair of wires to send data, wherein the communication method is called differential signaling.
In single-ended signaling, a bit is driven onto a board trace at a particular voltage level. In binary communication, where data is coded as a series of 1's and 0's, a 1 could be any voltage above a particular value, while a 0 could be any voltage below a certain value. The driver, therefore, when driving a 1, places a voltage step on the board trace. The performance of the complete communication system is a factor of the edge-rate and the voltage level that the driver drives onto the board trace. Generally, a faster edge-rate and a higher voltage level result in a higher performance system. In single-ended signaling, the receiving chip compares the voltage of the bit sent down the board trace against an internally generated reference voltage to resolve the identity of the bit. For example, in binary communication, the receiver resolves a bit to be a 1 if the voltage it receives is above the reference voltage, and a 0 if the voltage is below the reference voltage. A voltage step may be referred to as being composed of a set of sine waves having different frequencies. The edge rate of the voltage step can be a function of the set of frequencies, e.g., with higher frequencies resulting in a faster edge-rate.
High-speed single-ended signaling over relatively long board traces suffers from a number of important problems. The first problem is inter-symbol interference (ISI), where because of the high-speed nature of the signaling, the driver switches before the previous bit completely attains its direct current (DC) level, thereby attaining voltage levels on succeeding bits as a function of the previous bits. For example, if a driver has driven a 1 and then a 0, the voltage level attained by the 0 will be lower than the voltage level attained if the driver had driven two 1's followed by the 0. The second problem is low-pass characteristics of board traces that connect chips together, where the higher frequency components of a voltage step suffer greater losses than lower frequency components. Therefore, the edge-rate that a driver drives onto the bus degrades as it travels through a board trace. Third, the DC resistance of the long board trace also causes a voltage level loss of the edge that the driver drives onto the board trace.
Equalization is a technique that seeks to mitigate these three problems in wireline communication. The most common equalization scheme consists of drive-side pre-emphasis or zero-forcing schemes, where the driver drives a faster edge when it senses that it has driven a series of bits of the same value. Driver-side equalization, however, suffers from increased driver-caused switching noise on the driver power supply, thereby diminishing the performance achieved by this scheme. Traditional receiver-side equalization techniques, such as minimum-mean-square equalization or decision-feedback equalization schemes, require the use of analog filters and therefore are difficult to implement in a complementary metal oxide semiconductor (CMOS) device.
FIG. 1 illustrates a voltage waveform 100 in accordance with the prior art. The voltage waveform 100 can be received at a receiver pin when the data pattern is a “nominal” repeating pattern of 1010101. The receiver senses a high at 101, a low at 103, and a reference voltage at 105. As can be seen in FIG. 1, the speed of the signaling results in a bit time that is smaller than the time required for the voltage waveform to reach its steady-state value at 102 (i.e., the waveform 100 must transition at a point 104 because of the small bit time). In other words, the bit time of the signaling requires that the waveform transition before the voltage can settle to its steady-state value. The difference between the voltage received at the receiver pin for a 1 and the voltage that the receiver can recognize as a 1 is the voltage margin for the low to high transition (106). Similarly, the voltage margin for a high to low transition is shown at 108. Smaller voltage margins (106 and 108) result in higher bit error rate of the signaling interface, resulting in a lower performance interface.
FIG. 2 illustrates another voltage waveform (200) in accordance with the prior art. The voltage waveform 200 can be received at a receiver pin when the data pattern is 111101111 (i.e., there is a “lonely” 0 in the pattern). In FIG. 2, the voltage at the receiver pin has relatively more time to reach its steady-state value (204) and hence climbs to a “high” voltage that is higher than when the nominal pattern of alternating 0's and 1's is transmitted (such as in FIG. 1). When the “lonely” 0 is transmitted, the voltage of the signal line (204) does not go down to the level it went down to when the nominal data pattern was transmitted (such as in FIG. 1). This is because the high to low transition started at a voltage higher than in the nominal case. Thus, the voltage margin for the high to low transition (206) for a “lonely” 0 is diminished compared to the case of FIG. 1.
FIG. 3 illustrates a different voltage waveform (300) in accordance with the prior art. The voltage waveform 300 can be received at a receiver when a data pattern of the type 0001000 (i.e., containing a “lonely” 1) is transmitted. Here, the voltage margin for the low to high transition (304) is diminished when a waveform 300 transitions at a lower “low” value (306).